1. Field of the Invention
The present invention relates to a method of delay calculation in an integrated circuit and a timing analysis system using the same. More particularly, the present invention relates to a method of delay calculation in an integrated circuit, in which on-chip variation on a pair of paths is considered, and a timing analysis system using the same.
2. Description of the Related Art
Conventionally, when a delay time is calculated in case of timing verification (analysis) of an integrated circuit, a variation of delay time is calculated by multiplying a constant coefficient (delay time variation) with a delays time in paths from a branch, depending on a distribution of delay time. The constant coefficient (delay time variation) is obtained by adding a systematic component and a random component which are components of the delay time. The systematic component is defined as the maximum delay time under the consideration of one end to the other end in a chip, and the random component is calculated as a value per one stage on the path. The constant coefficient (delay time variation) is often not accurate.
FIG. 1 is a flow chart showing a conventional procedure of the timing analysis to an integrated circuit. Circuit data 100 of the integrated circuit (logic circuit) as a verification object is inputted and a delay time TP is calculated at each stage in a path (Step S801). The calculated delay time TP is stored as delay time data (Step S802).
Next, by multiplying a constant coefficient (delay time variation) with the calculated delay time, the delay time variation is calculated (Step S803), and stored as a delay time variation data (Step S804). Then, two paths logically related with each other are specified based on the circuit data 100 (Step S805), and the specified paths are stored as relative paths data (Step S806).
Next, the timing analysis of the SETUP analysis and the HOLD analysis to the relative paths is carried out using the variation of delay time (Step S807).
FIGS. 2 to 4 are diagrams to describe a conventional calculation method of the delay time in the paths of the integrated circuit. When there is not an on-chip variation between the paths, that is, the on-chip variation is ‘0’ as shown in FIG. 2, the delay time TP1 of one path P1 is a summation of the delay times TP1 i of respective stages i.
As shown in FIGS. 3 and 4, when the on-chip variation is not ‘0’, the delay time TP1 of the path P1 is a summation of the delay times TP1i in all thestages i on the path P1 in case of the minimum delay time (−α) or the maximum delay time (+α), as the minimum delay time TP1min or the maximum delay time TP1max. The minimum delay time TP1min and the maximum delay time TP1max are calculated by using a constant coefficient (α) as shown in the following equations (7).
                                          TP            ⁢                                                  ⁢                          1              min                                =                                    ∑                              i                =                1                            n                        ⁢                          {                              TP                ⁢                                                                  ⁢                                  1                  i                                *                                  (                                      1                    -                    α                                    )                                            }                                      ⁢                                  ⁢                              TP            ⁢                                                  ⁢                          1              max                                =                                    ∑                              i                =                1                            n                        ⁢                          {                              TP                ⁢                                                                  ⁢                                  1                  i                                *                                  (                                      1                    +                    α                                    )                                            }                                                          (        7        )            
For example, a conventional method of delay calculation is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-311877). In this conventional method, a maximum error which is set for every stage is multiplied with a calculated delay time for the stage to calculate the variation of delay time. This calculation method is the same as the above-mentioned method of multiplying the constant coefficient.
In this way, in the conventional delay time calculation method, the constant coefficient is multiplied to the delay time in the path from a branch. Therefore, it is not possible to carry out the calculation of the delay time with high accuracy to the pair of paths of a short distance and the paths with a large number of the stages. This is because the paths are not specified. For this reason, the stage count and the coordinate of each of the stages contained in the path cannot be specified, and the systematic component and the random component cannot be correctly calculated. Also, it is not possible to carry out an analysis with high reliability and the high accuracy in the integrated circuit timing analysis because the delay time with high accuracy cannot be obtained.